Digital signals, as opposed to analog signals, are readily transmitted and processed without substantially degrading the dynamic range, resolution and phase or linearity of these signals. For this reason, a wide range of commercial, industrial, scientific and military electronic systems convert analog signals to digital signals before transmitting or processing these signals. The rapid growth in the field of digital signal processing has sharply increased the need for high resolution analog-to-digital converters.
There are a number of existing classes of systems for analog-to-digital conversion or encoding. One such system is that of charge balance analog-to-digital converters. In a charge balance analog-to-digital converter (ADC), the input signal is balanced against a time average of a discretized feedback signal. During each clock cycle the ADC determines one bit of a 2**N bit conversion, where N, an integer, is the resolution of the ADC. A bipolar version of a charge balance ADC will require 2**(N-1) clock cycles to obtain each N-bit output. The standard bipolar charge balance ADC operates with a one bit digital-to-analog converter (DAC) in its feedback path. The difference (residue) between the external (input) analog signal and the DAC output is integrated and the sign of this integrated difference or residue is determined each clock cycle. If the integrated difference is positive, then the output of the feedback DAC is switched so as to drive the integrated difference negative. On the other hand, if the integrated difference is negative, then the output of the feedback DAC is switched so as to drive the integrated difference positive. A one bit accumulator (an up/down counter) is incremented in a direction which reflects the DAC output and the cycle is repeated. At the end of 2**(N-1) clock cycles, an N-bit word is accumulated in the up/down counter. It should be noted that it is the integrator which provides the time average that is necessary for such a charge balance ADC to function.
It has been suggested that the above described approach can be extended to high resolution analog-to-digital converter (HRADC) designs. This approach, however, will increase exponentially the required clock rate. For N-bit resolution, the required clock rate will be: ##EQU1## where FCLK is the required clock rate or frequency expressed in Hz, N is the resolution of the ADC and TC is the conversion time in seconds of the ADC, and where the symbol ** represents the exponentiation. The conversion time TC is the time in which the ADC system converts one sample of the analog input signal to a corresponding digital signal of a defined resolution. As an example, a 23 bit resolution, 1 millisecond (mSec) conversion time charge balance ADC will require a clock rate of 4.194 GHz. Such a high clock rate is very impractical.
The present invention addresses this shortcoming in part by increasing the resolution of the feedback path. By doing this the required clock rate for a given resolution is correspondingly decreased. As an example, if an M-bit resolution feedback path is used, M being an integer, the clock rate required to obtain an N-bit result will be: ##EQU2## Using the earlier example of a 23 bit resolution ADC system, a one mSec conversion time ADC with a 16-bit resolution feedback path, a clock rate of 128 KHz is required. This is certainly a more practical clock rate for use with a high resolution ADC. It will be noted that many different combinations of the feedback path resolution and the output resolution can be implemented within the spirit of this concept.
One serious problem still remains with designing an ADC based on the discussion above. The above example of a 23-bit resolution ADC using a 16-bit DAC will require a conversion time to 16-bits of resolution of 1/128 KHz or 7.8 .mu.Sec, which is quite fast.
The present invention eliminates this problem by providing an improvement on the concept of using a high resolution feedback circuit, the improvement comprising updating a higher (M-bit) resolution accumulator by the use of a lower (K-bit) resolution ADC, where part of the updating is achieved by amplifying only the difference or the residue between the external analog signal and the feedback signal.
The system of the invention provides a further improvement in resolution by successively adding the updated output of the M-bit accumulator into an N-bit (N &gt;M) accumulator. The system of the invention provides a further improvement in resolution by the use of a superimposed dither signal.